The present invention relates generally to the field of digital circuits, and more particularly to an output driver circuit with a well-controlled output impedance for driving signal lines in a high-speed digital system.
A signal line is a conductor used to transmit electrical signals between the various devices in an electronic system. Output driver circuits contained on each device are used to buffer signals originating from the device so that they may be driven onto the signal line.
For example, FIG. 1 illustrates a prior art digital system 1 including a plurality of devices 2, a signal transmitting device 3 and a signal line 4. The transmitting device 3 contains an output driver circuit 5 that generates a single-ended signal for output onto the signal line 4. The devices 2 are connected to the signal line 4 at various points to receive the signal. The signal line 4 includes a conductor 12, a termination resistor RT and a termination voltage VTerm. The termination resistor RT is connected to the end of the conductor 12 opposite the end connected to the output driver circuit 5. The termination resistor RT absorbs the incident signal, thereby preventing reflections of the signal from occurring at the end of the conductor 12. The termination resistor RT is also connected to the termination voltage VTerm. The termination voltage VTerm is used to raise the voltage of the conductor 12 to the high voltage level Voh.
An embodiment of the prior art digital system 1, a memory system 6, is shown in FIG. 2. Memory system 6 includes a plurality of dynamic random-access memories (DRAMs) 11, a clock chip 7, a clock line 8 and a memory controller 24. The clock chip 7 contains a clock driver circuit 9 that generates a single-ended clock signal for output onto the clock line 8. The clock line 8 includes a conductor 10 that passes through the memory controller 24 such that the conductor is divided into two portions: a CTM (clock to master) portion and a CFM (clock from master) portion. The CTM portion propagates the clock signal from the clock driver circuit 9 towards the memory controller 24 (the memory controller is the master device in the system). The CFM portion propagates the clock signal from the memory controller 24 towards the DRAMs 11. The DRAMs 11 are connected to both the CTM and CFM portions of the conductor 10. The conductor 10 is divided in this manner so that the clock signal can maintain a specific phase relationship with data signals (not shown) that are transmitted between the DRAMs 11 and the memory controller 24 as the signals propagate, regardless of whether the data signals are transmitted from the DRAMs to the memory controller or vice versa.
FIG. 3 shows a simplified electrical model of the clock driver circuit 9 and the clock line 8 in the memory system 6. In this model, the clock line 8 is represented by a transmission line of loaded impedance Z0. The loaded impedance Z0 includes the unloaded characteristic impedance Z0xe2x80x2 of the conductor 10 as well as the impedance of the DRAMs 11 and any other devices connected to the conductor. In order to minimize clock signal reflections at the end of the conductor 10, the resistance of the termination resistor RT is typically set to equal the loaded impedance Z0 of the conductor.
FIG. 4 is a waveform diagram illustrating the clock signal produced by the clock driver circuit 9 as a function of time. The clock signal has a high voltage level Voh and a low voltage level Vol, where Voh=VTerm, Vol=VTermxe2x88x922*(VTermxe2x88x92VRef), and VRef is a reference voltage. As a result, the clock signal has a voltage swing Vsw of Vsw=2*(VTermxe2x88x92VRef). The clock driver circuit 9 generates this waveform by operating as a switching current source, alternately turning on and off, sinking current every other half-cycle of the clock period. The clock signal is converted into an internal clock signal for use within the DRAMs 11 by circuitry (not shown) within the DRAMs. The circuitry generates the internal clock signal by comparing the voltage of the clock signal with the reference voltage Vref.
Unfortunately, the single-ended clock driver circuit 9 produces clock signals with relatively poor timing accuracy, i.e., xe2x80x9cclock jitter,xe2x80x9d especially at higher clock frequencies. There are several causes for the clock jitter. First, the voltage of the clock signal is dependent on the voltage VTerm, which typically suffers from significant xe2x80x9cnoisexe2x80x9d (i.e., rapid voltage fluctuations). The noise in the voltage VTerm may be caused, for example, by the switching on and off of numerous transistors in the system that are coupled to the voltage source. Second, the internal clock signal that is derived from the clock signal is dependent on the voltage VRef, which is also noise-prone for similar reasons.
A third cause for the clock jitter are the primary and secondary reflections of the clock signal produced on the clock line 8. Primary reflections are reflections of the clock signal produced along the conductor 10 by taps along the conductor at which the DRAMs 11 are connected and by the termination resistor RT. The reflections travel back towards the clock driver circuit 9. These reflections occur because of an impedance mismatch or discontinuity in the clock line 8 caused by the taps and/or the termination resistor. The primary reflections in turn cause secondary reflections to occur at the output of the clock driver circuit 9. The secondary reflections occur because the output impedance of the clock driver circuit 9, which acts as a high output impedance current source, is significantly greater than the loaded impedance Z0 of the clock line 8. The secondary reflections travel back down the conductor 10, thereby disturbing the clock signal waveform and causing jitter in the clock signal received by the DRAMs 11.
In view of the shortcomings of the prior art, it is an object of the present invention to provide a clock driver circuit that generates clock signals with minimal clock jitter despite the presence of noisy voltage supply signals.
It is another object of the present invention to provide a clock driver circuit that presents an output impedance that closely matches the loaded impedance of the clock line so as to minimize secondary reflections on the clock line.
More generally, it is an object of the present invention to provide an output driver circuit that generates a signal on a signal line with these characteristics.
In summary, the present invention is an output driver circuit for driving a signal onto a signal line. The output driver circuit provides an output impedance that closely matches the loaded impedance of the signal line at all times so as to minimize secondary reflections on the signal line. The output driver circuit may be used as a clock driver circuit to drive a clock signal onto a clock line. In this application, the output driver circuit provides a clock signal with minimal clock jitter despite the presence of noisy voltage supplies.
The output driver circuit of the present invention includes at least one driver circuit and a passive network. The passive network is coupled to the output of the driver circuit and includes an output corresponding to each driver circuit for coupling to a signal line conductor. The passive network, which may be composed of a network of resistors, is configured to limit the variation in the output impedance of the output driver circuit.
The output driver circuit of the present invention includes embodiments that generate a single-ended signal and other embodiments that generate a differential signal. For the single-ended signal embodiments, the output driver circuit includes a single driver circuit coupled to a passive network. The passive network includes a series resistor and a parallel resistor. The series resistor is connected between the output of the driver circuit and the output of the passive network. The parallel resistor is connected between the output of the passive network and a voltage supply, such as VDD or Gnd. The passive network may optionally include a capacitor connected between the parallel resistor and the voltage supply to provide an AC ground.
For the differential signal embodiments, the output driver circuit includes first and second driver circuits and a passive network that includes first and second outputs. In a first embodiment, the passive network includes a first series resistor connected between the output of the first driver circuit and the first output of the passive network, a first parallel resistor coupled between the first output of the passive network and a differential ground node, a second series resistor connected between the output of the second driver circuit and the second output of the passive network and a second parallel resistor coupled between the second output of the passive network and the differential ground node.
In a second differential signal embodiment of the output driver circuit, the first and second driver circuits each comprise a p-channel transistor and an n-channel transistor in an inverter-like configuration, a first series resistor connected between the drain of the p-channel transistor and the output of the inverter and a second series resistor connected between the drain of the n-channel transistor and the output of the inverter. In this embodiment, the passive network includes a first parallel resistor coupled between the output of the first driver circuit and a differential ground node and a second parallel resistor coupled between the output of the second driver circuit and the differential ground node.
In a third differential signal embodiment of the output driver circuit, the first and second driver circuits each comprise a p-channel transistor and an n-channel transistor in an inverter configuration and the passive network includes a first parallel resistor coupled between the output of the first driver circuit and a differential ground node and a second parallel resistor coupled between the output of the second driver circuit and the differential ground node. In this embodiment, the gates of the p-channel and n-channel transistors of the first and second driver circuits are driven with signals having voltages such that the transistors operate in a saturation or cutoff region of operation only. The output driver circuit may further include predrivers to generate these signals.